In a semiconductor memory such as a SRAM, a word address decoder circuit is provided which generates select/unselect signals for appropriately selecting a plurality of memory cells in the same row of a memory cell array (e.g., those cells which are connected to the same word line), all while the remaining cells remain unselected. The address decoder circuit receives word address signals, in true and complement form, (e.g. n bits;) and generates one select signal among 2.sup.n combinations of the address signals.
High speed and large capacity SRAMs play a key role in the development of modern high performance computer systems. To achieve this goal, BICMOS circuits which merge bipolar and CMOS technology are highly desirable to provide both bipolar and CMOS devices with the best performance/cost trade off.
As far as address decoder circuits are concerned, the present tendency is to combine a high speed low power multistage bipolar address decoder circuit with a CMOS or BICMOS driver in order to drive the heavy capacitive loads on the word lines of the memory array, typically comprised of CMOS 6-device SRAM cells.
It is well known that Current Mode Logic (CML) technology provides an extensive family of logic circuits, and in particular address decoder circuits with high speed operation at moderately low power levels. This is also true for its various derivatives or variants: e.g. Differential Cascode Current Switch (DCCS) logic, Emitter Coupled Logic (ECL), etc. With respect to DCCS logic, one may refer to the article: "Generation of multiple single-phase outputs from a single DCCS decode circuit" by M. E. Cohen et al, published in IBM Technical Disclosure Bulletin, Vol. 26, No. 7A, December 1983, pp 3503-3504.
A good example of such a multistage bipolar address decoder in CML technology is given in the article: "BICMOS circuit technology for a high speed SRAM", by T. Douseki et al published in the IEEE Journal of Solid State Circuits, Vol. 23, No. 1, Feb. 88, pp 68-73.
This article shows a way to design a bipolar address decoder circuit for a BICMOS memory. The decoder circuit may be understood as being composed of three circuit stages connected in cascade: a predecoding circuit of the ECL collector dotting type (CD), a level shifting circuit of the standard emitter follower type (EF), and a main decoding circuit called a series gate circuit (SG) in CML technology.
The CD circuit is used as the first layer of decoding. According to the CD circuit, it is not necessary to explicitly generate the true and complement address signals because the address receiver is included in the pre-decoder. However, this is not a definite advantage. True and complement address signals are generally available in a current switch environment. Alternatively, it is also possible to replace the complement address signals by a fixed reference voltage if supply and signal voltages are adequate.
For each address signal, a receiver of the current switch type generates current information corresponding to true and complement values. Therefore, instead of using a voltage, a current provides the pre-decoding information. The collectors are all dotted together and a decoded address will correspond to no current flow in any of them. The main disadvantage or drawback of this solution is that a kind of current mirror must be used in the CD circuit and this can lead to poor control on "low" voltage which corresponds to non-selection. A second drawback resides in the fact that the input capacitance of the CD circuit will be very high since transistors must be connected in parallel to provide the currents representative of a true/complement address which of course increases the number of transistors used in the circuit implementation.
The purpose of the emitter follower (EF) circuit is to generate pre-decoded signals with a number of Vbe DC shifts (depending on the number of diodes) in order to drive the series gate (SG) circuit that follows so that it operates as a level converter. This construction has some inconveniences, because it does not provide an efficient solution in optimizing the SG circuit.
The third decoding layer consists of a series gate circuit. Because the signals that drive the series gate circuit have already been predecoded by the collector dotting circuit, a differential tree where more than 2 transistors are connected in each branch can be used. Although this construction reduces the number of layers in the tree, it has a significant drawback in that the common emitter nodes are more heavily loaded, which in turn, results in slowing down current switching. In addition, it is clear that the up or "high" level depends on Vcc (minus a number of Vbe's), while the down or "low" level is referenced to ground. Finally, the saturation control of the series gate circuit is poor, and becomes even more acute when supply voltages are reduced.
All these circuits are biased between a positive supply voltage (VCC=0V) and a negative supply voltage (VEE=-5.2V) and all use standard current sources connected to VEE.
Seen as a whole, the disclosed three stage address decoder is power consuming in that there is no means provided to cut down the DC power in any stage of the decoder. This therefore causes a continuous consumption of power in the quiescent state, even if the circuits are not selected. Secondly, it has a limited flexibility and adaptability to different memory sizes and organizations because of the close interrelationships existing between the three circuits which in turn, makes it difficult to increase the number of tree levels. Further, there is a risk the output transistors of the series gate circuit saturating which leads to slower switching.